The present disclosure relates to circuits adjusting interchannel signal skew, and more particularly to interchannel skew adjustment circuits suitable for parallel transmission interfaces such as low voltage differential signaling (LVDS) interfaces.
LVDS interfaces are widely used as interfaces for data transmission among image processing LSIs inside digital televisions, and between image processing LSIs and display drivers. In recent years, the amount of information transmission of digital televisions has increased to accept 3D, 4K2K, and 8K4K, and an increase in the speed and bandwidths of LVDS interfaces have been required.
An LVDS interface transmits a clock signal (e.g., a single clock signal of 135 MHz) and a plurality of data signals (e.g., 20 data signals of 945 Mbps) at the same time, and belongs to interfaces for clock forward (i.e., source synchronous) parallel transmission. This type of interface may be an extremely simple circuit, which latches the plurality of data signals using the sent clock signal. However, the interface is generally regarded as not suitable for increasing speed, since interchannel skew between a clock and data, and between data and data becomes a bottleneck.
One solution to this problem of the interchannel skew is a clock embedded interface which sends data signals only and not a clock signal. This type of interface extracts the clock signal from the data signal in each channel, and thus the problem of the interchannel skew does not occur. However, a clock recovery circuit needs to be mounted in each channel at a receiver. This increases the complexity, the area, the cost, and the power consumption of the circuits at the receiver. In particular, receiver chips such as display drivers are placed at the panel and thus need to have a high breakdown voltage. Thus, a normal miniaturized process cannot be used, thereby increasing the area.
To address the problem, not a clock embedded interface but a source synchronous interface is used. In addition, to solve the problem of the interchannel skew, an interface receives and latches signals of channels sent from a sender circuit at a receiver circuit, feeds back the result to the sender circuit, and adjusts delay of the signals at the sender to correctly latch the signals at the receiver, is suggested. (See, for example, D1: Japanese Patent Publication No. 2002-189698.) Another interface adjusts interchannel skew by controlling the delay amount of a data delay circuit based on a frame signal contained in each signal of channels before delay adjustment. (See, for example, D2: Japanese Patent Publication No. H11-341102.) Yet another interface includes an analog phase detection circuit between channels of a receiver circuit, and adjusts the delay amount of an analog delay line to eliminate an interchannel phase difference. (See, for example, D3: Yuxiang Zheng, et al., A 5 Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13 um CMOS, Digest of Symposium on VLSI Circuits, pp 71-72, June, 2010.)
The following requirements are placed on an interchannel skew adjustment circuit used for a source synchronous parallel transmission interface represented by an LVDS interface.
(1) Signals are transmitted in one direction only from a sender to a receiver. There is no signal fed back from the receiver to the sender, and thus a sender end or a receiver end needs to meet the specification of interchannel skew. This requires a mechanism automatically adjusting skew at the sender or the receiver.
(2) Since the number of channels is large, skew needs to be adjusted in a small area and at low power consumption. Therefore, skew is preferably adjusted using not an analog delay line but a digital circuit.
(3) Skew needs to be finely adjusted in each channel so that a person in charge of arranging a set of a television device, etc., performs optimum settings including sending and receiving. This requires a mechanism less influenced by process, voltage, and temperature (PVT) variations and generating constant delay.
The skew adjustment circuit shown in D1 requires a signal fed back from the receiver, and skew cannot be adjusted at the sender only. On the other hand, the skew adjustment circuit shown in D3 adjusts skew by at the receiver only. However, since an analog delay line is used, a large circuit area and high power consumption are concerned. The skew adjustment circuit shown in D2 feeds forward the frame signal to control the delay amount of each channel. Where the data delay circuit has characteristic variations, the output timing of the signals of the channels after the delay adjustment may be off. In addition, in each of the above-described conventional art, if the delay circuit has PVT variations, constant delay is difficult to generate, thereby degrading the accuracy of the skew adjustment.
Therefore, there is a need for an interchannel skew adjustment circuit, which adjusts interchannel signal skew using a sender or a receiver only in a small circuit area and at low power consumption. Furthermore, there is a need for a highly accurate interchannel skew adjustment circuit, which is less influenced by PVT variations.